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ARM Cortex-A75

ARM Cortex-A75
General information
Launched2017
Designed byARM Holdings
Max. CPU clock rateto 3.0 GHz 
Cache
L1 cache128 KB (64 KB I-cache with parity, 64 KB D-cache) per core
L2 cache256–512 KB
L3 cache1–4 MB
Architecture and classification
ApplicationMobile
Network Infrastructure
Automotive designs
Servers
Instruction setARMv8.2-A
Physical specifications
Cores
  • 1–8 per cluster, multiple clusters
Products, models, variants
Product code name
  • Prometheus
History
PredecessorsARM Cortex-A73
ARM Cortex-A72
ARM Cortex-A17
SuccessorARM Cortex-A76

The ARM Cortex-A75 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings's Sophia design centre. The Cortex-A75 is a 3-wide decode out-of-order superscalar pipeline.[1] The Cortex-A75 serves as the successor of the Cortex-A73, designed to improve performance by 20% over the A73 in mobile applications while maintaining the same efficiency.[2]

  1. ^ "Cortex-A75". Cortex-A75. ARM Holdings. Retrieved 10 July 2017.
  2. ^ Humrick, Matt (29 May 2017). "Exploring Dynamiq and ARM's New CPUs". Anandtech. Retrieved 10 July 2017.

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