Nios V

Nios V
Designer	Altera/Intel
Bits	32-bit
Design	RISC
Type	Load–store
Encoding	Variable
Branching	Compare-and-branch
Endianness	Little
Page size	4 KiB
Open	No
Registers
General-purpose	16; 32; (Includes one always-zero register)
Floating point	32; (Optional; width depends on available extensions)

Nios V is a 32-bit embedded processor based on the RISC-V instruction set architecture (ISA) designed specifically for the Altera family of field-programmable gate array (FPGA).

Nios V is a successor to Altera's Nios II embedded processor, which had been the company's embedded processor offering for the previous 2 decades, but was discontinued by Intel in 2023.^[1] The migration to the RISC-V ISA transitions Altera's embedded processor offering away from a proprietary ISA to an open architecture with support for industry standard software development and compilation tools.

^ "Intel is discontinuing IP ordering codes listed in PDN2312 for Nios® II IP". Intel. Retrieved 2025-01-22.

[1] "Intel is discontinuing IP ordering codes listed in PDN2312 for Nios® II IP". Intel. Retrieved 2025-01-22.

[1]