Multiple patterning

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Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Hence additional exposures would be needed, or else positioning patterns using etched feature sidewalls (using spacers) would be necessary.

Even with single exposure having sufficient resolution, extra masks have been implemented for better patterning quality such as by Intel for line-cutting at its 45nm node^[1] or TSMC at its 28nm node.^[2] Even for electron-beam lithography, single exposure appears insufficient at ~10 nm half-pitch, hence requiring double patterning.^[3][4]

Double patterning lithography was first demonstrated in 1983 by D. C. Flanders and N. N. Efremow.^[5] Since then several double patterning techniques have been developed such as self alignment double patterning (SADP) and a litho-only approach to double patterning.^[6][7]

Pitch double-patterning was pioneered by Gurtej Singh Sandhu of Micron Technology during the 2000s, leading to the development of 30-nm class NAND flash memory. Multi-patterning has since been widely adopted by NAND flash and random-access memory manufacturers worldwide.^[8][9]