Semiconductor device fabrication |
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MOSFET scaling (process nodes) |
Future
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In semiconductor manufacturing, the 3nm process is the next die shrink after the 5 nm MOSFET (metal–oxide–semiconductor field-effect transistor) technology node. South Korean chipmaker Samsung started shipping its 3 nm gate all around (GAA) process, named 3GAA, in mid-2022.[1][2] On 29 December 2022, Taiwanese chip manufacturer TSMC announced that volume production using its 3 nm semiconductor node (N3) was under way with good yields.[3] An enhanced 3 nm chip process called "N3E" may have started production in 2023.[4] American manufacturer Intel planned to start 3 nm production in 2023.[5][6][7]
Samsung's 3 nm process is based on GAAFET (gate-all-around field-effect transistor) technology, a type of multi-gate MOSFET technology, while TSMC's 3nm process still uses FinFET (fin field-effect transistor) technology,[8] despite TSMC developing GAAFET transistors.[9] Specifically, Samsung plans to use its own variant of GAAFET called MBCFET (multi-bridge channel field-effect transistor).[10] Intel's process (dubbed "Intel 3", without the "nm" suffix) will use a refined, enhanced and optimized version of FinFET technology compared to its previous process nodes in terms of performance gained per watt, use of EUV lithography, and power and area improvement.[11]
Node name | Gate pitch | Metal pitch | Year |
---|---|---|---|
5 nm | 51 nm | 30 nm | 2020 |
3 nm | 48 nm | 24 nm | 2022 |
2 nm | 45 nm | 20 nm | 2025 |
1 nm | 40 nm | 16 nm | 2027 |
The term "3 nanometer" has no direct relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3nm node is expected to have a contacted gate pitch of 48 nanometers, and a tightest metal pitch of 24 nanometers.[12]
However, in real world commercial practice, 3nm is used primarily as a marketing term by individual microchip manufacturers (foundries) to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.[13][14] There is no industry-wide agreement among different manufacturers about what numbers would define a 3nm node.[15] Typically the chip manufacturer refers to its own previous process node (in this case the 5nm node) for comparison. For example, TSMC has stated that its 3nm FinFET chips will reduce power consumption by 25–30% at the same speed, increase speed by 10–15% at the same amount of power and increase transistor density by about 33% compared to its previous 5 nm FinFET chips.[16][17] On the other hand, Samsung has stated that its 3nm process will reduce power consumption by 45%, improve performance by 23%, and decrease surface area by 16% compared to its previous 5 nm process.[18] EUV lithography faces new challenges at 3 nm which lead to the required use of multipatterning.[19]
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