Semiconductor device fabrication |
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MOSFET scaling (process nodes) |
Future
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In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the "5 nm" process as the MOSFET technology node following the "7 nm" node. In 2020, Samsung and TSMC entered volume production of "5 nm" chips, manufactured for companies including Apple, Marvell, Huawei and Qualcomm.[1][2]
The term "5 nm" has no accurate relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors being five nanometers in size anymore. Historically, this number used to represent gate length, but it started deviating from the actual length to smaller numbers (by intel) around 2011.[3] According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 5 nm chip's gate length is going to be 18nm.[4] However, in real world commercial practice, "5 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption compared to the previous 7 nm process.[5][6]
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