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ARM Cortex-A57

ARM Cortex-A57
General information
Launched2012
Designed byARM Holdings
Cache
L1 cache80 KiB (48 KiB I-cache with parity, 32 KiB D-cache with ECC) per core
L2 cache512 KiB to 2 MiB
L3 cachenone
Architecture and classification
Instruction setARMv8-A
Physical specifications
Cores
  • 1–4 per cluster, multiple clusters[1]
Products, models, variants
Product code name(s)
  • Atlas
History
Successor(s)ARM Cortex-A72

The ARM Cortex-A57 is a central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A57 is an out-of-order superscalar pipeline.[1] It is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).

  1. ^ a b "Cortex-A57 Processor". ARM Holdings. Retrieved 2014-02-02.

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