Arrow Lake (microprocessor)

Arrow Lake

Launched	October 24, 2024
Designed by	Intel
Manufactured by	Intel TSMC
Fabrication process	TSMC N3B TSMC N5P TSMC N6
Codename(s)	ARL
Platform(s)	Desktop Mobile
Branding
Brand name(s)	Core Ultra
Generation	Series 2
Socket(s)	LGA 1851 BGA 2114[1]
Instructions & Architecture
Instructions set	x86
Instructions	x86-64
P-core architecture	Lion Cove
E-core architecture	Skymont
Cores
Peak core clock	Up to 5.7 GHz
P-core L0 cache	48 KB data (per core)
P-core L1 cache	256 KB (per core): 64 KB instructions 192 KB data
E-core L1 cache	96 KB (per core): 64 KB instructions 32 KB data
P-core L2 cache	3 MB (per core)
E-core L2 cache	4 MB (per cluster)
P-core L3 cache	3 MB (per core)
E-core L3 cache	3 MB (per cluster)
Graphics
Graphics architecture	Xe-LPG Xe-LPG+
Execution Units	Up to 64 EUs
Xe Cores	Up to 8 Xe Cores
Peak graphics clock	2.0 GHz
NPU
Architecture	NPU 3720
TOPS	13
Memory Support
Type	DDR5-6400
Memory channels	2 channels
Maximum capacity	192 GB
I/O
PCIe support	PCIe 5.0
PCIe lanes	20 PCIe 5.0 lanes 4 PCIe 4.0 lanes
DMI version	DMI 4.0 x8
History
Predecessor	Meteor Lake
Variant	Lunar Lake
Successor	Panther Lake

Arrow Lake is the codename for Core Ultra Series 2 processors designed by Intel, released on October 24, 2024. It follows on from Meteor Lake which saw Intel move from monolithic silicon to a disaggregated MCM design. Meteor Lake was limited to a mobile release while Arrow Lake includes both socketable desktop processors and mainstream and enthusiast mobile processors. Core Ultra 200H and 200HX series mobile processors will follow in early 2025.^[2] Arrow Lake desktop CPUs integrated Thunderbolt 4 and USB4 in the CPU, which allowed it to not be limited by PCIe 3 speeds and use simple retimers instead. The chipset has the same maximum five integrated USB 3.2 2x2, and is Thunderbolt 5 ready if a discrete board is used.^[3] The integrated GPU added HDMI 2.1 FRL 48 gbit/s (just like mobile Meteor Lake) and a variable refresh rate. CU-DIMM DDR5 memory support was added and is needed for optimal performance.^[4][5]