Clipper architecture

Clipper

Intergraph Clipper C4 (C400) CPU
Designer	Fairchild Semiconductor Intergraph
Bits	32-bit
Introduced	1986; 39 years ago (1986)
Design	RISC-like

The Clipper architecture is a 32-bit reduced instruction set computer (RISC)-like central processing unit (CPU) instruction set architecture designed by Fairchild Semiconductor. The architecture had little market success: the only computer manufacturers to create major product lines using Clipper processors were Intergraph and High Level Hardware, although Opus Systems offered a product based on the Clipper as part of its Personal Mainframe range.^[1] The first processors using the Clipper architecture were designed and sold by Fairchild, but the division responsible for them was subsequently sold to Intergraph in 1987; Intergraph continued work on Clipper processors for use in its own systems.^[2]

The Clipper architecture used a simplified instruction set compared to earlier complex instruction set computer (CISC) architectures, but it did incorporate some more complex instructions than were present in other contemporary RISC processors. These instructions were implemented in a so-called Macro Instruction read-only memory (ROM) within the Clipper CPU. This scheme allowed the Clipper to have somewhat higher code density than other RISC CPUs.