Dataflow architecture

Dataflow architecture is a dataflow-based computer architecture that directly contrasts the traditional von Neumann architecture or control flow architecture. Dataflow architectures have no program counter, in concept: the executability and execution of instructions is solely determined based on the availability of input arguments to the instructions,^[1] so that the order of instruction execution may be hard to predict.

Although no commercially successful general-purpose computer hardware has used a dataflow architecture, it has been successfully implemented in specialized hardware such as in digital signal processing, network routing, graphics processing, telemetry, and more recently in data warehousing, and artificial intelligence (as: polymorphic dataflow^[2] Convolution Engine,^[3] structure-driven,^[4] dataflow scheduling^[5]). It is also very relevant in many software architectures today including database engine designs and parallel computing frameworks.^{[citation needed]}

Synchronous dataflow architectures tune to match the workload presented by real-time data path applications such as wire speed packet forwarding. Dataflow architectures that are deterministic in nature enable programmers to manage complex tasks such as processor load balancing, synchronization and accesses to common resources.^[6]

Meanwhile, there is a clash of terminology, since the term dataflow is used for a subarea of parallel programming: for dataflow programming.

^ Veen, Arthur H. (December 1986). "Dataflow Machine Architecture". ACM Computing Surveys. 18 (4): 365–396. doi:10.1145/27633.28055. S2CID 5467025. Retrieved 5 March 2019.
^ Maxfield, Max (24 December 2020). "Say Hello to Deep Vision's Polymorphic Dataflow Architecture". Electronic Engineering Journal. Techfocus media.
^ "Kinara (formerly Deep Vision)". Kinara. 2022. Retrieved 2022-12-11.
^ "Hailo". Hailo. Retrieved 2022-12-11.
^ Lie, Sean (29 August 2022). Cerebras Architecture Deep Dive: First Look Inside the HW/SW Co-Design for Deep Learning. Cerebras (Report).
^ "HX300 Family of NPUs and Programmable Ethernet Switches to the Fiber Access Market". EN-Genius (Press release). June 18, 2008. Archived from the original on 2011-07-22.

[architecture-1] Veen, Arthur H. (December 1986). "Dataflow Machine Architecture". ACM Computing Surveys. 18 (4): 365–396. doi:10.1145/27633.28055. S2CID 5467025. Retrieved 5 March 2019.

[2] Maxfield, Max (24 December 2020). "Say Hello to Deep Vision's Polymorphic Dataflow Architecture". Electronic Engineering Journal. Techfocus media.

[3] "Kinara (formerly Deep Vision)". Kinara. 2022. Retrieved 2022-12-11.

[4] "Hailo". Hailo. Retrieved 2022-12-11.

[5] Lie, Sean (29 August 2022). Cerebras Architecture Deep Dive: First Look Inside the HW/SW Co-Design for Deep Learning. Cerebras (Report).

[EN-Genius-6] "HX300 Family of NPUs and Programmable Ethernet Switches to the Fiber Access Market". EN-Genius (Press release). June 18, 2008. Archived from the original on 2011-07-22.

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