Physical verification

Physical verification is a process whereby an integrated circuit layout (IC layout) design is verified via EDA software tools to ensure correct electrical and logical functionality and manufacturability. Verification involves design rule check (DRC), layout versus schematic (LVS), XOR (exclusive OR), antenna checks and electrical rule check (ERC).^[1]

^ A. Kahng, et al.: VLSI Physical Design: From Graph Partitioning to Timing Closure, ISBN 978-3-030-96414-6, doi:10.1007/978-3-030-96415-3, p. 9.

[PDbook_p10-1] A. Kahng, et al.: VLSI Physical Design: From Graph Partitioning to Timing Closure, ISBN 978-3-030-96414-6, doi:10.1007/978-3-030-96415-3, p. 9.

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