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POWER, PowerPC, and Power ISA architectures |
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NXP (formerly Freescale and Motorola) |
IBM |
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IBM/Nintendo |
Other |
Related links |
Cancelled in gray, historic in italic |
General information | |
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Launched | 2005 |
Discontinued | Present |
Marketed by | IBM, Sony, Microsoft |
Designed by | IBM |
Common manufacturer | |
Performance | |
Max. CPU clock rate | 2.8 GHz to 3.2 GHz |
Cache | |
L1 cache | 32 KB instruction + 32 KB data |
Architecture and classification | |
Application | Gaming Console, HPC |
Technology node | 90 nm to 45 nm |
Microarchitecture | PPU |
Instruction set | PowerPC 2.02 |
Physical specifications | |
Cores |
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GPUs | Xenos, in the XCGPU variant. |
Products, models, variants | |
Variant | |
History | |
Successor | IBM A2 |
The Power Processing Element (PPE) comprises a Power Processing Unit (PPU) and a 512 KB L2 cache. In most instances the PPU is used in a PPE. The PPU is a 64-bit dual-threaded in-order PowerPC 2.02 microprocessor core designed by IBM for use primarily in the game consoles PlayStation 3 and Xbox 360, but has also found applications in high performance computing in supercomputers such as the record setting IBM Roadrunner.
The PPU is used as a main CPU core in three different processor designs:
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