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| Designer | ARC International PLC |
|---|---|
| Bits | 32-bit, 64-bit |
| Introduced | 1996 |
| Version | ARCv3 |
| Design | RISC |
| Type | Register–Register |
| Encoding | Variable (16- and 32-bit) |
| Branching | Compare and branch |
| Endianness | Bi |
| Extensions | APEX user-defined instructions |
| Registers | |
| 16 or 32 including SP user can increase to 60 | |
ARC (Argonaut RISC Core) embedded system processors are a family of 32-bit and 64-bit reduced instruction set computer (RISC) central processing units (CPUs) originally designed by ARC International.
ARC processors are configurable and extensible for a wide range of uses in system on a chip (SoC) devices, including storage, digital home, mobile, automotive, and Internet of things (IoT) applications. They have been licensed by more than 200 organizations and are shipped in more than 1.5 billion products per year.[1]
ARC processors employ the 16-/32-bit ARCompact compressed instruction set instruction set architecture (ISA) that provides good performance and code density for embedded and host SoC applications.
- ^ "Overcoming the power/performance paradox in processor IP". Tech Design Forums. Retrieved 13 August 2014.
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