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ARM Cortex-A73

ARM Cortex-A73
General information
Launched2016
Designed byARM Holdings
Max. CPU clock rateto 2.8 GHz 
Cache
L1 cache96–128 KiB (64 KiB I-cache with parity, 32–64 KiB D-cache) per core
L2 cache1–8 MiB
L3 cacheNone
Architecture and classification
ApplicationMobile
Instruction setARMv8-A
Physical specifications
Cores
  • 1–4 per cluster, multiple clusters
Products, models, variants
Product code name(s)
  • Artemis
History
Predecessor(s)ARM Cortex-A72
ARM Cortex-A17
Successor(s)ARM Cortex-A75

The ARM Cortex-A73 is a central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings' Sophia design centre. The Cortex-A73 is a 2-wide decode out-of-order superscalar pipeline.[1] The Cortex-A73 serves as the successor of the Cortex-A72, designed to offer 30% greater performance or 30% increased power efficiency.[2]

  1. ^ "Cortex-A73 Processor". ARM Holdings. Retrieved 2017-03-28.
  2. ^ Cutress, Ian; Tallis, Billy (29 May 2016). "Computex 2016: ARM Press Conference Live Blog". Anandtech. Retrieved 29 March 2017.

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