 | This article needs additional citations for verification. (July 2018) |
| Designer | Altera |
|---|---|
| Bits | 32-bit |
| Design | RISC |
| Endianness | Little-Endian |
| Open | No |
| Registers | |
| General-purpose | 32 |
Nios II is a 32-bit embedded processor architecture designed specifically for the Altera family of field-programmable gate array (FPGA) integrated circuits. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from digital signal processing (DSP) to system-control.
Nios II is a successor to Altera's first configurable 16-bit embedded processor Nios, introduced in 2000.[1]
- ^ Altera. "Nios II Embedded Processor Backgrounder" (PDF).
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