Physical Address Extension

In computing, Physical Address Extension (PAE), sometimes referred to as Page Address Extension,[1] is a memory management feature for the x86 architecture. PAE was first introduced by Intel in the Pentium Pro, and later by AMD in the Athlon processor.[2] It defines a page table hierarchy of three levels (instead of two), with table entries of 64 bits each instead of 32, allowing these CPUs to directly access a physical address space larger than 4 gigabytes (232 bytes).

The page table structure used by x86-64 CPUs when operating in long mode further extends the page table hierarchy to four or more levels, extending the virtual address space, and uses additional physical address bits at all levels of the page table, extending the physical address space. It also uses the topmost bit of the 64-bit page table entry as a no-execute or "NX" bit, indicating that code cannot be executed from the associated page. The NX feature is also available in protected mode when these CPUs are running a 32-bit operating system, provided that the operating system enables PAE.

  1. ^ Dual-Core Intel® Xeon® Processor 2.80 GHz Specification Update (PDF). Intel Corporation. October 2006. p. 18.
  2. ^ "Appendix E". AMD Athlon™ Processor x86 Code Optimization Guide (PDF) (Revision K ed.). AMD, Inc. February 2002. p. 250. Retrieved 2017-04-13. A 2-bit index consisting of PCD and PWT bits of the page table entry is used to select one of four PAT register fields when PAE (page address extensions) is enabled, or when the PDE doesn't describe a large page.

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