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Verilog

Verilog
ParadigmStructured
Designed byPrabhu Goel, Phil Moorby and Chi-Lai Huang
DeveloperIEEE
First appeared1984 (1984)
Stable release
IEEE 1800-2023 / 6 December 2023 (2023-12-06)
Typing disciplineStatic, weak
Filename extensions.v, .vh
Websitehttps://ieeexplore.ieee.org/document/10458102
Dialects
Verilog-AMS
Influenced by
Pascal, Ada, C, Fortran
Influenced
SystemVerilog

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.[citation needed] It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits.[1] In 2009, the Verilog standard (IEEE 1364-2005) was merged into the SystemVerilog standard, creating IEEE Standard 1800-2009. Since then, Verilog has been officially part of the SystemVerilog language. The current version is IEEE standard 1800-2023.[2]

  1. ^ Nielsen AA, Der BS, Shin J, Vaidyanathan P, Paralanov V, Strychalski EA, Ross D, Densmore D, Voigt CA (2016). "Genetic circuit design automation". Science. 352 (6281): aac7341. doi:10.1126/science.aac7341. PMID 27034378.
  2. ^ Cite error: The named reference IEEE2023 was invoked but never defined (see the help page).

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