7 nm process

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Semiconductor device fabrication
MOSFET scaling (process nodes)
020 µm – 1968 010 µm – 1971 006 µm – 1974 003 µm – 1977  1.5 µm – 1981 001 µm – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 090 nm – 2003 065 nm – 2005 045 nm – 2007 032 nm – 2009 028 nm – 2010 022 nm – 2012 014 nm – 2014 010 nm – 2016 007 nm – 2018 005 nm – 2020 003 nm – 2022
Future 002 nm ~ 2024
Half-nodes Density CMOS Device (multi-gate) Moore's law Transistor count Semiconductor Industry Nanoelectronics
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In semiconductor manufacturing, the "7 nm" process is a term for the MOSFET technology node following the "10 nm" node, defined by the International Roadmap for Devices and Systems (IRDS), which was preceded by the International Technology Roadmap for Semiconductors (ITRS). It is based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology. As of 2021, the IRDS Lithography standard gives a table of dimensions for "7 nm"^[1], with a few given below:

The 2021 IRDS Lithography standard is a backward-facing document, as the first volume production of a "7 nm" branded process, as Taiwan Semiconductor Manufacturing Company (TSMC) began production of 256 Mbit SRAM memory chips using a "7 nm" process called N7 in June 2016,^[2] before Samsung began mass production of their "7 nm" process called 7LPP devices in 2018.^[3] These process nodes had the same approximate transistor density as Intel's "10 nm Enhanced Superfin" node, later rebranded "Intel 7."^[4]

Since at least 1997, the length scale of a process node has not referred to any particular dimension on the integrated circuits, such as gate length, metal pitch, or gate pitch, as new lithography processes no longer uniformly shrank all features on a chip. By the late 2010s, the length scale had become a commercial name^[5] that indicated a new generation of process technologies, without any relation to physical properties.^[6][7][8] Previous ITRS and IRDS standards had insufficient guidance on process node naming conventions to address the widely varying dimensions on a chip, leading to divergence between how foundries branded their lithography and the actual dimensions their process nodes achieved.

The first mainstream "7 nm" mobile processor intended for mass market use, the Apple A12 Bionic, was released at Apple's September 2018 event.^[9] Although Huawei announced its own "7 nm" processor before the Apple A12 Bionic, the Kirin 980 on August 31, 2018, the Apple A12 Bionic was released for public, mass market use to consumers before the Kirin 980. Both chips were manufactured by TSMC.^[10]

In 2019,^[11] AMD released their "Rome" (EPYC 2) processors for servers and datacenters, which are based on TSMC's N7 node^[12] and feature up to 64 cores and 128 threads. They also released their "Matisse" consumer desktop processors with up to 16 cores and 32 threads. However, the I/O die on the Rome multi-chip module (MCM) is fabricated with the GlobalFoundries' 14 nm (14HP) process, while the Matisse's I/O die uses the GlobalFoundries' "12 nm" (12LP+) process. The Radeon RX 5000 series is also based on TSMC's N7 process.