Designer | University of California, Berkeley |
---|---|
Bits | 32, 64, 128 |
Introduced | August 6, 2014[1] |
Version | |
Design | RISC |
Type | Load–store |
Encoding | Variable |
Branching | Compare-and-branch |
Endianness | Little[2]: 9 [a] |
Page size | 4 KiB |
Extensions |
|
Open | Yes, royalty free |
Registers | |
General-purpose |
|
Floating point |
|
RISC-V[b] (pronounced "risk-five"[2]: 1 ) is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, RISC-V is provided under royalty-free open-source licenses. Many companies are offering or have announced RISC-V hardware; open source operating systems with RISC-V support are available, and the instruction set is supported in several popular software toolchains.
The project began in 2010 at the University of California, Berkeley. There are now members in over 70 countries contributing and collaborating to define RISC-V open specifications. RISC-V International, the non-profit managing RISC-V, is currently headquartered in Switzerland.[5][6]
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