Back İntel quickpath interconnect texnologiyası Azerbaijani Intel QuickPath Interconnect Catalan Intel QuickPath Interconnect German Intel QuickPath Interconnect Spanish Intel QuickPath Interconnect Estonian QuickPath Finnish QuickPath Interconnect French Intel QuickPath Interconnect HE Intel QuickPath Interconnect Italian インテル QuickPath インターコネクト Japanese
 | This article needs to be updated. (January 2014) |
The Intel QuickPath Interconnect (QPI)[1][2] is a point-to-point processor interconnect developed by Intel which replaced the front-side bus (FSB) in Xeon, Itanium, and certain desktop platforms starting in 2008. It increased the scalability and available bandwidth. Prior to the name's announcement, Intel referred to it as Common System Interface (CSI).[3] Earlier incarnations were known as Yet Another Protocol (YAP) and YAP+.
QPI 1.1 is a significantly revamped version introduced with Sandy Bridge-EP (Romley platform).[4]
QPI was replaced by Intel Ultra Path Interconnect (UPI) in Skylake-SP Xeon processors based on LGA 3647 socket.[5]
- ^ "An Introduction to the Intel QuickPath Interconnect" (PDF). Intel Corporation. January 30, 2009. Retrieved June 14, 2011.
- ^ DailyTech report Archived 2013-10-17 at the Wayback Machine, retrieved August 21, 2007
- ^ Eva Glass (May 16, 2007). "Intel CSI name revealed: Slow, slow, quick quick slow". The Inquirer. Archived from the original on June 10, 2012. Retrieved September 13, 2013.
{{cite news}}: CS1 maint: unfit URL (link) - ^ David Kanter (2011-07-20). "Intel's Quick Path Evolved". Realworldtech.com. Retrieved 2014-01-21.
- ^ SoftPedia: Intel Plans to Replace Xeon with Its New Skylake-Based “Purley” Super Platform
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