Xeon

Xeon

Logo since 2024
General information
Launched	June 1998; 25 years ago (June 1998)
Marketed by	Intel
Designed by	Intel
Common manufacturer(s)	Intel TSMC
Performance
Max. CPU clock rate	400 MHz to 5.3 GHz
FSB speeds	100 MT/s to 1.6 GT/s
QPI speeds	4.8 GT/s to 24 GT/s
DMI speeds	2.0 GT/s to 16 GT/s
Data width	Up to 64 bits
Address width	Up to 64 bits
Virtual address width	Up to 57 bits
Cache
L1 cache	Up to 80 KB per core
L2 cache	Up to 2 MB per core
L3 cache	Up to 320 MB per socket
L4 cache	Up to 64 GB HBM2e[1]
Architecture and classification
Application	Servers Workstations Embedded systems
Technology node	250 nm to Intel 3 and TSMC N5
Microarchitecture	P6 NetBurst Core Nehalem Westmere Sandy Bridge Ivy Bridge Haswell Broadwell Skylake Sunny Cove Cypress Cove Golden Cove Raptor Cove Redwood Cove Crestmont
Instruction set	IA-32, x86-64
Instructions	MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, AVX2, FMA3, AVX-512, AVX-VNNI, TSX, AES-NI, CLMUL, RDRAND
Extensions	SGX, SHA, TXT, VT-x, VT-d
Physical specifications
Cores	Up to 64 cores per socket (up to 128 threads per socket)
Memory (RAM)	Up to 4 TB and 8 channels per socket Up to DDR5-5600 with ECC support
GPU(s)	Intel Graphics Technology (some models only)
Co-processor	Xeon Phi (2010-2020)
Socket(s)	Slot 2 Socket 603 Socket 604 LGA 775 LGA 771 LGA 1156 LGA 1366 LGA 1155 LGA 2011 LGA 1150 LGA 2011-3 LGA 1151 LGA 1151v2 LGA 1200 LGA 1700 LGA 2066 LGA 3647 LGA 4189 LGA 4677 LGA 7529
Products, models, variants
Brand name(s)	Xeon E Xeon D Xeon w3[2] Xeon w5[2] Xeon w7[2] Xeon w9[2] Xeon Bronze Xeon Silver Xeon Gold Xeon Platinum Xeon Max[3]
Variant(s)	Itanium (2001-2020)
History
Predecessor(s)	Pentium Pro
Support status
Supported

Xeon (/ˈziːɒn/; ZEE-on) is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded markets. It was introduced in June 1998. Xeon processors are based on the same architecture as regular desktop-grade CPUs, but have advanced features such as support for error correction code (ECC) memory, higher core counts, more PCI Express lanes, support for larger amounts of RAM, larger cache memory and extra provision for enterprise-grade reliability, availability and serviceability (RAS) features responsible for handling hardware exceptions through the Machine Check Architecture (MCA). They are often capable of safely continuing execution where a normal processor cannot due to these extra RAS features, depending on the type and severity of the machine-check exception (MCE). Some also support multi-socket systems with two, four, or eight sockets through use of the Ultra Path Interconnect (UPI) bus, which replaced the older QuickPath Interconnect (QPI) bus.